How to use various resources of a Xilinx FPGA

[hobbyiclearner]

Hi,

I was going through the user guide of Spartan 3 FPGA (ug331). It mentions several internal resources; such as clock buffers, digital clock managers, block RAMs, carry and multiplier logic, I/O blocks etc. Is there any book/ other resource to learn how to use these. I am basically looking for practicals which I can try out. The user guide section is 400 pages, too big to read through for any of these blocks.:-D

Thanks,
Hobbyiclearner.

 

[ads-ee]

The user guide section is 400 pages, too big to read through for any of these blocks.:-D

If you want to learn how to use those blocks then you should read those 400 pages. I've done that with every generation of part since the 3000 series parts.

The other option is to pester everyone on edaboard asking for help with using each resource (basically asking forum members to read the user guide for you).:thumbsdown:

Instead if you ask questions about something you don't understand in those 400 pages and require clarification, then I'm sure someone can help with that.:thumbsup:

If you are not willing to read the documentation supplied by the vendor, then perhaps you shouldn't be using these kind of parts and should try using a CPLD, which will have significantly less documentation that you will need to read.

 

[KlausST]

Hi,

If you are not willing to read the documentation supplied by the vendor, then perhaps you shouldn't be using these kind of parts

Yes. Thats my opinion, too.

These are very complex parts, if you want to use them you need to understand them.

Kaus

 

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FPGA - Olympic diving and swim competition pool.

ASIC - the ocean

If FPGA documentation is daunting then start at the kiddie pool end of the programmable spectrum

 

[hobbyiclearner]

If you want to learn how to use those blocks then you should read those 400 pages. I've done that with every generation of part since the 3000 series parts.

The other option is to pester everyone on edaboard asking for help with using each resource (basically asking forum members to read the user guide for you).:thumbsdown:

.

I do not want anyone to read the 400 pages for me... I wanted to know if anyone is aware of any practical manual regarding these blocks (maybe you will like to recheck my original post). In case there is such a manual / resource, then I would go through it myself.

 

[TrickyDicky]

The reference manual IS the manual to read.

There are many tutorials out there on how to write code to infer more generic type blocks (registers, adders, multipliers, etc etc) that will carry over to all FPGA devices, but for device specific things that you cannot infer, you have to read the manual.

 

[ads-ee]

(maybe you will like to recheck my original post).

I have, many times. Every time this sticks out like a sore thumb.

The user guide section is 400 pages, too big to read through for any of these blocks.:-D

How about I substitute something else for "user guide" e.g.
"Oh, the driver's handbook is 100 pages long, that's too big to read to understand the individual rules of the road." A question like that would make me think you shouldn't be driving at all.

If you had stated something like The 400 page user guide has a daunting amount of information, are there any short simple tutorials that touch on the most used basics?". That might have pointed you to sites like:
https://www.fpga4fun.com/
https://www.asic-world.com/examples/verilog/index.html
Both sites will show you how to write code for the most used features that are typically inferred and you can examine the results of synthesis and implementation using the schematic view, to understand exactly how the RTl gets translated to the device features.

If you have specific features you want to use that can't be inferred then you should read those specific sections on that feature.

 

[vGoodtimes]

Read the intro for each chapter first. Then read the application sections for each chapter. Read more about any topic that interest you.

Skip section 2, as it will be outdated compared to ISE/Planahead documentation.

 

[hobbyiclearner]

OK... so which fpga's user guide should I read (spartan 3,4,5,6, virtex 2 etc). I want to learn the common features available in all present day FPGA's.

Thanks,
Hobbyiclearner

 

[vGoodtimes]

Read any of the Xilinx GT* guides -- GTP, GTX, GTH etc... They are all excellent references to the basics of high-speed serial IO.

Read (google) the "Altera Advanced Synthesis Cookbook". The concepts are good for any FPGA.

You should always start with a refresher on the FPGA fabric for a new device. FPGAs are not really field programmable "gate" arrays. Gate-level design and optimization often makes no sense because the primitive components are 6LUTs with some extra logic.
(Likewise, sandbox as much as you can. premature optimization can result in unreadable, needlessly complex code. You should be able to see a faster/better solution in case the sane one isn't good enough, but don't start with a "I have to re-invent everything" approach!)

 

[hobbyiclearner]

Read any of the Xilinx GT* guides -- GTP, GTX, GTH etc... They are all excellent references to the basics of high-speed serial IO.

Read (google) the "Altera Advanced Synthesis Cookbook". The concepts are good for any FPGA.

You should always start with a refresher on the FPGA fabric for a new device. FPGAs are not really field programmable "gate" arrays. Gate-level design and optimization often makes no sense because the primitive components are 6LUTs with some extra logic.

Thanks for the tips. My query was which xilinx fpga user guide to read. Also, are you recommending altera than xilinx? The GTP, GTX etc seem to be advanced level user guides suitable for virtex series.

Thanks,
Hobbyiclearner

 

[vGoodtimes]

IMO, the Altera "advanced synthesis guide" is a masterpiece worthy of reading even if you never use Altera devices.

I was suggesting the fastest FPGA route in the case where you have no specific goals. The GT* guides do a good job explaining high speed serial/bonded interfaces, and thus an important part of modern digital design.