How to use Uart vhdl code provide by Xilinx?

[gn01167661]

Aye I am currently trying to useXAPP341, from Xilinx to transmitt a Zero(00110000) to PC
here is my code

my clk is 50Mhz
and baud rate i am using 19200 Hz

ENTITY main IS port(
clk :in std_logic;
tx  :out std_logic
);
END main;

architecture Behavioral of main is

	COMPONENT txmit
	PORT(
		rst : IN std_logic;
		clk16x : IN std_logic;
		wrn : IN std_logic;
		din : IN std_logic_vector(7 downto 0);          
		tbre : OUT std_logic;
		tsre : OUT std_logic;
		sdo : OUT std_logic
		);
	END COMPONENT;

	SIGNAL rst :  std_logic:='1';
	SIGNAL clk16x :  std_logic:='0';
	SIGNAL wrn :  std_logic:='0';
	SIGNAL din :  std_logic_vector(7 downto 0);
	SIGNAL tbre :  std_logic;
	SIGNAL tsre :  std_logic;
	SIGNAL sdo :  std_logic;
	SIGNAL COUNTER :  std_logic_vector(7 downto 0):= (others => '0');
	SIGNAL COUNTER2 :  std_logic_vector(2 downto 0):= (others => '0');

BEGIN

	clk_process:process(clk)
	begin
	if(clk'event and clk='1')then
	Counter<=Counter+1;
		if(Counter>="10100011")then
		clk16x<=NOT(clk16x);
		Counter<=(others=>'0');
	   end if;
	end if;
	end process clk_process;
	
	
	RST_process:process(clk16x)
	begin
	if(clk16x'event and clk16x='1')then
		if (COUNTER2<="010")then
		COUNTER2<=COUNTER2+1;
		
			if((COUNTER2>="001")and (COUNTER2<"010"))then
			RST<='0';
			wrn<='1';
			elsif(COUNTER2>="010")then

			wrn<='0';
			end if;
		end if;
	end if;
	end process RST_process;
	
	uut: txmit PORT MAP(
		rst => rst,
		clk16x => clk16x,
		wrn => wrn,
		din => "00110000",
		tbre => tbre,
		tsre => tsre,
		sdo => tx
	);
END Behavioral;

but it keep sending out random character on hyperTerminal, can anyone tell me what did i do wrong ?

---------- Post added at 15:21 ---------- Previous post was at 15:18 ----------

This is the code I am using provided by Xilinx ... please please help me

library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;

entity txmit is
port (rst,clk16x,wrn : in std_logic ;
	din : in std_logic_vector(7 downto 0) ;
	tbre : out std_logic ;
	tsre : out std_logic ;
	sdo  : out std_logic 
) ;
end txmit ;

architecture v1 of txmit is

signal clk1x_enable : std_logic ;
signal tsr : std_logic_vector (7 downto 0) ;
signal tbr : std_logic_vector (7 downto 0) ;
signal parity :  std_logic ;
signal clkdiv :  unsigned (3 downto 0) ;
signal clk1x :  std_logic ;
signal no_bits_sent :  unsigned (3 downto 0) ;
signal wrn1 :  std_logic ;
signal wrn2 :  std_logic ;

begin

process (rst,clk16x)
begin
if rst = '1' then
wrn1 <= '1' ;
wrn2 <= '1' ;
elsif clk16x'event and clk16x = '1' then
wrn2 <= wrn1 ;
wrn1 <= wrn ;
end if ;
end process ;


process (rst,clk16x)
begin
if rst = '1' then
clk1x_enable <= '0' ;
tbre <= '0' ;
elsif clk16x'event and clk16x = '1' then
if wrn1 = '0' and wrn2 = '1' then 
tbre <= '0' ;
clk1x_enable <= '1' ;
elsif std_logic_vector(no_bits_sent) = "0010" then
tbre <= '1' ;
elsif std_logic_vector(no_bits_sent) = "1101" then
clk1x_enable <= '0' ;
end if ;
end if ;
end process ;

process (rst,wrn)
begin
if rst = '1' then
tbr <= (others => '0') ;
elsif wrn'event and wrn = '0' then
tbr <= din ;
end if ;
end process ;

process (rst,clk16x,clk1x_enable)
begin
if rst = '1' then
clkdiv <=  "0000" ;
elsif clk16x'event and clk16x = '1' then
if clk1x_enable = '1' then
clkdiv <= clkdiv + "0001" ;
end if ;
end if ;
end process ;

clk1x <= clkdiv(3) ;

process (rst,clk1x,no_bits_sent,tbr)
begin
if rst = '1' then 
sdo <= '1' ;
tsre <= '1' ;
tsr <= "00000000" ;
parity <= '1' ;
elsif clk1x'event and clk1x = '1' then
if std_logic_vector(no_bits_sent) = "0001" then
tsr <= tbr ;
tsre <= '0' ;
elsif std_logic_vector(no_bits_sent) = "0010" then
sdo <= '0' ;
elsif std_logic_vector(no_bits_sent) >= "0011" and std_logic_vector(no_bits_sent) <= "1010" then
tsr <= tsr(6 downto 0) & '0' ;
sdo <= tsr(7) ;
parity <= parity xor tsr(7) ;
end if ;
end if ;
end process ;


process (rst,clk1x,clk1x_enable)
begin
if rst = '1' or clk1x_enable = '0' then
no_bits_sent <= "0000" ;
elsif clk1x'event and clk1x = '1' then
if clk1x_enable = '1' then
no_bits_sent <= no_bits_sent + "0001" ;
end if ;
end if ;
end process ;

end ;

 

[barry]

My GUESS is that your 16x clock frequency is wrong. Your clk16x SHOULD be 307.2KHz for 19.2K baud. You don't show where you're generating clk16x in your code.