How to use TSMC 0.18u inductor for CMOS LC VCO design?

[EEstudent]

TSMC 0.18u inductor- VCO

I am trying to design a CMOS LC VCO for 5 GHz using TSMC 0.18u process.

1) But I discovered that the inductor provided in the library has a minimum value of 2.3 nH. For 5 GHz operation, I need a smaller value of inductor than this. How do I do this??? If I connect two inductors in parallel, this would increase the area significantly.


2) I am using a MOS varactor to tune the VCO. One end of the varactor is connected to the control voltage and the other end to the VCO output, which oscillates at a certain frequency. This means for a fixed control voltage, within one cycle, the voltage across the varactor chnages continously, which means the capacitance keeps changing every instant. How can we analyze this and how do we get a fixed frequency in this case, since the capacitance is changing at every instant?

thanks

 

[iamlog]

Re: TSMC 0.18u inductor- VCO

Have you got the answer to your first question?

As far as the 2nd question, I just read a paper: JSSC 2003 Vol.38, No.8 pp1325-1332. It looks as long as you are using accumulation mode MOS varators, it is ok.

 

[fun.zhao]

Re: TSMC 0.18u inductor- VCO

first question:
you can use bondwire as the inductor.
Bondwire's Q is higher than spiral inductor.

 

[EEstudent]

Re: TSMC 0.18u inductor- VCO

Hi Abbas,

what is the name of the paper you mentioned.

thanks

 

[a.abbas]

Re: TSMC 0.18u inductor- VCO

i attached the paper for u in my last post. it's name is "Large-Signal Analysis of MOS Varactors in CMOS -Gm LC VCOs"
good luck