instantiation of srl16 failed
Hi,
How to use the vlog to comple the library, please tell me in detail, i need to finish this project within today,please guide me.
kanimozhi
Added after 35 minutes:
Hi,
This is a one of the program file in my project , In this I am using MUXF5 primitive , but when i simulate it i m getting error which i was mentioned in my previous thread, please some one help me how to initiate the and use the MUXF5 primitive in my program, which library i should initiate in my program and how to use it in my verilog file
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:00:40 01/12/2009
// Design Name:
// Module Name: SB6
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
/* Sbox 6 */
module SB6(addr,da,db);
input [1:6] addr;
output [1:4] da;
output [1:4] db;
reg [1:4] d0;
reg [1:4] d1;
reg [1:4] d2;
reg [1:4] d3;
always @(addr) begin
case (addr[2:5])
0: d0 = 12;
1: d0 = 1;
2: d0 = 10;
3: d0 = 15;
4: d0 = 9;
5: d0 = 2;
6: d0 = 6;
7: d0 = 8;
8: d0 = 0;
9: d0 = 13;
10: d0 = 3;
11: d0 = 4;
12: d0 = 14;
13: d0 = 7;
14: d0 = 5;
15: d0 = 11;
endcase
end
always @(addr) begin
case (addr[2:5])
0: d1 = 10;
1: d1 = 15;
2: d1 = 4;
3: d1 = 2;
4: d1 = 7;
5: d1 = 12;
6: d1 = 9;
7: d1 = 5;
8: d1 = 6;
9: d1 = 1;
10: d1 = 13;
11: d1 = 14;
12: d1 = 0;
13: d1 = 11;
14: d1 = 3;
15: d1 = 8;
endcase
end
always @(addr) begin
case (addr[2:5])
0: d2 = 9;
1: d2 = 14;
2: d2 = 15;
3: d2 = 5;
4: d2 = 2;
5: d2 = 8;
6: d2 = 12;
7: d2 = 3;
8: d2 = 7;
9: d2 = 0;
10: d2 = 4;
11: d2 = 10;
12: d2 = 1;
13: d2 = 13;
14: d2 = 11;
15: d2 = 6;
endcase
end
always @(addr) begin
case (addr[2:5])
0: d3 = 4;
1 : d3 = 3;
2 : d3 = 2;
3 : d3 = 12;
4 : d3 = 9;
5 : d3 = 5;
6 : d3 = 15;
7 : d3 = 10;
8 : d3 = 11;
9 : d3 = 14;
10: d3 = 1;
11: d3 = 7;
12: d3 = 6;
13: d3 = 0;
14: d3 = 8;
15: d3 = 13;
endcase
end
// mux the first two together in F5 muxes
MUXF5 s10 ( .I0(d0[1]), .I1(d1[1]), .S(addr[6]), .O(da[1]) );
MUXF5 s11 ( .I0(d0[2]), .I1(d1[2]), .S(addr[6]), .O(da[2]) );
MUXF5 s12 ( .I0(d0[3]), .I1(d1[3]), .S(addr[6]), .O(da[3]) );
MUXF5 s13 ( .I0(d0[4]), .I1(d1[4]), .S(addr[6]), .O(da[4]) );
// mux the second two together in F5 muxes
MUXF5 s20 ( .I0(d2[1]), .I1(d3[1]), .S(addr[6]), .O(db[1]) );
MUXF5 s21 ( .I0(d2[2]), .I1(d3[2]), .S(addr[6]), .O(db[2]) );
MUXF5 s22 ( .I0(d2[3]), .I1(d3[3]), .S(addr[6]), .O(db[3]) );
MUXF5 s23 ( .I0(d2[4]), .I1(d3[4]), .S(addr[6]), .O(db[4]) );
endmodule
regards
kanimozhi.m