how to use -source_latency_included option in set_input_delay?

[LAORUAN]

what does these sentence mean?

Input delays can already include clock source latency. By default the clock source latency of the related clock is added to the input delay value,but when the -source_latency_included option is specified, the clock source latency is not added because it was factored into the input delay value.

If -source_latency_included option is used, it means I should add the source latency into input delay or I should not add the source latency into input delay(Timequest will add add the source latency into input delay)?

Any help will be appreciated. Thank you.

 

[axcdd]

With source_latency_included you should add source delay.
You can read about different parameters in *.sdc constraints on "Constraining Designs for Synthesis and Timing Analysis: A Practical Guide to Timing Analysis" book

 

[LAORUAN]

Thank you for your reply.

I have read the on the "set_input_delay" on "Constraining Designs for Synthesis and Timing Analysis: A Practical Guide to Timing Analysis" book.

But I still have a doubt on that.

As we can see, the input delay includes the source latency without source_latency_included.

 

[sharath666]

Basically you have to account for the source latency of the clock.
1.If you use this option it means you are specifying it explicitly.
2.If you don't use this option, you are including this delay in the input_delay value.
I think it would be better if you use this option and specify the delay explicitly. This would make your constraints look more realistic and give a better picture of your design.

 

[LAORUAN]

Basically you have to account for the source latency of the clock.
1.If you use this option it means you are specifying it explicitly.
2.If you don't use this option, you are including this delay in the input_delay value.
I think it would be better if you use this option and specify the delay explicitly. This would make your constraints look more realistic and give a better picture of your design.

Thank you.

Gernerally， I use the set_clock_latency to set the latency of the clock of FPGA.
Do you mean that I have to set the latency of the clock of external device?

 

[sharath666]

I was talking about the clock coming to the FPGA. As a FPGA designer you can set constraints only on the clocks coming into the FPGA. So you can set input_delay constraints on these clocks.
Clocks of the external device are outside your scope..