How to use $setup,$hold and $width system tasks in verilog??

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aswin123

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verilog $width

How to use $setup,$hold and $width system tasks in verilog.

in which block we can use these statements (i mean always block or specify block)

can anybody expalin me with example
 

$setup verilog

use them like this(specify block is located between module and endmodule)

specify
specparam
tIFCLK=20.83,
tSRD=12.7,
tRDH=3.7,
tSWR=12.1,
tWRH=3.6,
tSFD=3.2,
tFDH=4.5,
tSFA=25,
tFAH=10;
$setup(slrd,posedge clk,tSRD);
$hold(slrd,posedge clk,tRDH);
$setup(slwr,posedge clk,tSWR);
$hold(slwr,posedge clk,tWRH);
$setup(data,posedge clk,tSFD);
$hold(data,posedge clk,tFDH);
$setup(fifo_addr,posedge clk,tSFA);
$setup(fifo_addr,posedge clk,tFAH);
endspecify
 

verilog $setup

any verilog books can solve your problem
 

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