wisemonkey
Junior Member level 3
Hi everyone,
I've been reading about DFT (Scan in particular). The more I read about it, I keep finding ways to insert scan chain in design with the help of synthesis tools (which is good).
However I wanted to know if that is the only way or we can insert scan chain while writing a verilog code as well? I'm not sure how anyone would break ~200 bit register (assuming its in design) and make it sequential/serial.
All suggestions/opinions are appreciated
Thanks![Smile :) :)](data:image/gif;base64,R0lGODlhAQABAIAAAAAAAP///yH5BAEAAAAALAAAAAABAAEAAAIBRAA7)
I've been reading about DFT (Scan in particular). The more I read about it, I keep finding ways to insert scan chain in design with the help of synthesis tools (which is good).
However I wanted to know if that is the only way or we can insert scan chain while writing a verilog code as well? I'm not sure how anyone would break ~200 bit register (assuming its in design) and make it sequential/serial.
All suggestions/opinions are appreciated
Thanks