How to use scan (in code?)

[wisemonkey]

Hi everyone,
I've been reading about DFT (Scan in particular). The more I read about it, I keep finding ways to insert scan chain in design with the help of synthesis tools (which is good).
However I wanted to know if that is the only way or we can insert scan chain while writing a verilog code as well? I'm not sure how anyone would break ~200 bit register (assuming its in design) and make it sequential/serial.

All suggestions/opinions are appreciated

Thanks

 

[lostinxlation]

You can do it manually if you choose to do so.
Till a little over 10 years ago, there was no decent DFT tool and we all did stitch the scan chains manually in the netlist.

You can also write a script in perl or any other languages to stitch the scan chain. I haven't done it for insernal scan, but made a script to stitch the boundary scan chain in perl. However, if you want to take care of any other things such as reset/clock bypassing, it would be challenging.

 

[wisemonkey]

You can do it manually if you choose to do so.
Till a little over 10 years ago, there was no decent DFT tool and we all did stitch the scan chains manually in the netlist.

You can also write a script in perl or any other languages to stitch the scan chain. I haven't done it for insernal scan, but made a script to stitch the boundary scan chain in perl. However, if you want to take care of any other things such as reset/clock bypassing, it would be challenging.

ok so if I understand it properly:
write a perl code to
1. search for f/f in netlist (something like DFF2x etc.)
2. replace it with muxed f/f or mux and a f/f

and thanks for the suggestion