multiple clocks vhdl
In the testbench the frequency is not the problem.
In one data pipeline the clock frequency have to be a single one.
When 2 pipelines with different frequencies are connected together
2 situations occur.
When one frequency is equal to multiplied second frequency,
or the frequencies have small common divident
then
both pipelines must have a single frequency which is highest of them,
or can be divided to both of them.
When the frequencies have the great common divident,
then
an FIFO buffer is introduced which consists of 2,3 or higher latch stages.
For example f1=2 MHz, f2=3 MHz then
the common frequency is 6 MHz which is their divident.