nashafi
Member level 1
vhdl multiple clocks
Hi,
I am designing a decimation filter for a data standard like ardis or mobitex.
since there is a lot of upsampling and downsampling going on so i need multiple clocks all the way in my pipeline.
How can i write different clocks for my test bench. I am confused about how can i associate different frequencies with different components in my top file
Thanks,
-Nauman
Hi,
I am designing a decimation filter for a data standard like ardis or mobitex.
since there is a lot of upsampling and downsampling going on so i need multiple clocks all the way in my pipeline.
How can i write different clocks for my test bench. I am confused about how can i associate different frequencies with different components in my top file
Thanks,
-Nauman