Has anyone used MOS capacitance in any of the design? AS the literature says, there is some non-linearization in the C-V characterisation. Any comments to improvise>?
do you mean to use a MOS transistor as a capacitor?
if yes. it is simple, just tie drain and source together and body to GND or VDD for nmos or pmos. then you'll have a capacitor between gate and drain-source (tied together). take care in this configuration source and drain voltages should not go below GND or above VDD. you can also connect the body to drain and source instead of supply rails. each of these configurations have different C-V characteristics.
it is easy to simulate these mos-caps in hspice and see the characteristic
Thanks for the reply...I have tried characterising both the configurations...I need to use the case with back-gate connected to gnd for nmos...In this case do we have any compensation techniques to eradicate non-linearity in CV chs.?? I have found many such techniques for the configuration where bulk or the back-gate is taken as terminal..
Thanks for the reply...I have tried characterising both the configurations...I need to use the case with back-gate connected to gnd for nmos...In this case do we have any compensation techniques to eradicate non-linearity in CV chs.?? I have found many such techniques for the configuration where bulk or the back-gate is taken as terminal..
oh! sorry i don't have any information about compensating the varactor non-linearity. by the way there is regions in C-V charac of a varactor that capacitance value is constant (not changing with voltage) you can use those regions by applying the appropriate voltage across the MOS varactor.
regards.