how to use JTAG port as normal IO

[ZFDok]

the xilinx xcr3032 ,its JTAG port can be used as normal IO ports ,but i don't know how to constraint it in ISE, who can teach me what to do?

 

[srilu]

Just disable the JTAG option while compiling.
(check for menu options to do this on ISE)
then JTAG pins will be configured as normal IO.

-srilu

 

[ZFDok]

Very thanhs !but i don't find the menu option for JTAG, but i found one "reserve ISP pins" option in fitting properties ,is it?

 

[sp]

without the JTAG... how u gonna program the code into the chip?...

sp

 

[Black Jack]

without the JTAG... how u gonna program the code into the chip?...

sp

The Port Enable pin should be held low during power up and during normal operation. If the device has been programmed such that the JTAG port pins are used as I/O, a High logic level signal placed on the Port Enable
pin will revert those pins back to their normal JTAG function.

XAPP343 - In-System Programming of XPLA3 Devices

 

[BrainStorm_BG]

You can't use the JTAG pins as I/O's ... they are reserved pins ...

 

[ZFDok]

i don't know how to constraint it in ISE compile environment, not real circuit board, who can help me?

 

[tkbits]

Very thanhs !but i don't find the menu option for JTAG, but i found one "reserve ISP pins" option in fitting properties ,is it?

Uncheck it or select "No" and discover if that works.

 

[Black Jack]

You can't use the JTAG pins as I/O's ... they are reserved pins ...

See docs from XILINX!
We talk about XCR3032

 

[soccer]

Just disable the JTAG option while synthsising.

 

[wjx197733]

Do not use JTEG as I/O. Programmer we write can download to FPGA or CPLK only through JTEG

 

[rongo024]

Write MCUCSR = 0x80 twice at the beginning of your code

 

[vyshnavi]

Please let me know how to write code for jtag interface. please give me the code.

this is for simulation only.

i am not using any hardware. i just want to simulate and write a test bench to test it.

please help me.

urgent.

:idea: