how to use inout signals in UVM Methodology

[kansagaratushar]

Hi,

I know how to use inout signals in systemverilog simple testbench. But How can I use inout signals in UVM testbench Environment?

In which class Should I define & drive another "reg" signal with control variable.....?
How can I define in interface and Top module?

Any Help are thankful to me.

 

[dave_59]

You might want to read my DVCon paper on connecting class based testbenches to RTL: **broken link removed**

as well as my blog explaining some of the fundamental differences between nets and variables: https://go.mentor.com/wire-vs-reg