How to use Floating Point Operator...

[TrickyDicky]

you use the library just by calling it in:

library ieee_proposed;
use ieee_proposed.fixed_float_types.all;
use ieee_proposed.fixed_pkg.all; --this is the library you really want

and including the source files for the ieee_proposed library in your project.


And the std_logic warnings are because you probably forgot to include std_logic_1164 in your design.

 

[ablam]

you need to convert the 12 bit integer to floating point in a convert block. why do you need floating point anyway? fpgas work better with fixed point.

Hi,

How can i use float_pkg_c.vhdl in my implementatiotin which makes use of floating point numbers.Is this the code synthesizable if we use the same?I copied
library ieee_proposed;
use ieee_proposed.float_pkg_c.vhdl.all;to my code
also copied the package codes also

but it gives me error like ieee_proposed is not declared.Give me a solution plz.THANKS IN ADVANCE

 

[TrickyDicky]

you need to create an ieee_proposed library.
But if you're doing floating point, I wouldnt use these libraries - they do no give you any pipelining. You should be using the Vendor's floating point IP cores instead.,

 

[ablam]

you use the library just by calling it in:


Can u tel me how to convert this code for floating point division or do u have any floating point division code other than open cores .Plz help me.I need it urgently


library IEEE;
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FMUL2 is
port(CLK, St: in std_logic;
F1, E1, F2, E2: in std_logic_vector(3 downto 0);
F: out std_logic_vector(6 downto 0);
E: out std_logic_vector(4 downto 0));
--V, done: out std_logic);
end FMUL2;


architecture BEHAVE of FMUL2 is
signal A, B, C: std_logic_vector(3 downto 0); -- F regs
signal compout, addout:std_logic_vector(3 downto 0);
alias M: std_logic is B(0);
signal X, Y: std_logic_vector(4 downto 0); -- E regs
signal Load, Adx, SM8, RSF, LSF: std_logic; -- Main
signal AdSh, Sh, Cm, Mdone,sdone: std_logic; -- Mult
signal PS1, NS1: integer range 0 to 4;-- Main state
signal State, Nextstate: integer range 0 to 4;-- Mult
signal V, done: std_logic;
begin



main_control: process(PS1, St , Mdone, X, A, B)
begin
Load <= '0'; Adx <= '0'; NS1 <= 0; SM8 <= '0';
RSF <= '0'; LSF <= '0'; V <= '0'; --done <= '0';

case PS1 is
when 0 =>
if St = '1' then
Load <= '1';
NS1 <= 1;
done<='0';
end if;
when 1 =>
Adx <= '1';
NS1 <= 2;

when 2 =>
if Mdone = '1' then
if A = 0 then -- FZ
SM8 <= '1';
elsif A = 4 and B = 0 then -- FV
RSF <= '1';
elsif A(2) = A(1) then -- not Fnorm
LSF <= '1';
end if;
NS1 <= 3;
else
NS1 <= 2;
end if;
when 3 =>
sdone <= '1';
if X(4) /= X(3) then -- EV
V <= '1';
end if;
if ST = '0' and sdone='1' then
NS1 <= 0;
else NS1<=4;
end if;
when 4 =>
done <= sdone;
NS1<=4;
end case;
end process main_control;



mul2c: process(State, Adx, M)
begin
AdSh <= '0'; Sh <= '0'; Cm <= '0'; Mdone <= '0';
Nextstate <= 0;
case State is
when 0 =>
if Adx = '1' then
if M = '1' then
AdSh <= '1';
else
Sh <= '1';
end if;
Nextstate <= 1;
end if;
when 1 | 2 =>
if M = '1' then
AdSh <= '1';
else
Sh <= '1';
end if;
Nextstate <= State + 1;
when 3 =>
if M = '1' then
Cm <= '1';
AdSh <= '1';
else
Sh <='1';
end if;
Nextstate <= 4;
when 4 =>
Mdone <= '1';
Nextstate <= 0;
end case;
end process mul2c;


compout <= not C when Cm = '1' else C;
addout <= A + compout + ("000" & Cm);





datapath: process(CLK)
begin
if CLK = '1' and CLK'event then
PS1 <= NS1;
State <= Nextstate;
if Load = '1' then
X <= E1(3) & E1;
Y <= E2(3) & E2;
A <= "0000";
B <= F2;
C <= F1;
end if;

if ADX = '1' then
X <= X + Y;
end if;
if SM8 = '1' then
X <= "11000";
end if;
if RSF = '1' then
A <= '0' & A(3 downto 1);
B <= A(0) & B(3 downto 1);
X <= X + 1;
end if;
if LSF = '1' then
A <= A(2 downto 0) & B(3);
B <= B(2 downto 0) & '0';
X <= X - 1;
end if;
if AdSh = '1' then
A <= compout(3) & addout(3 downto 1);
B <= addout(0) & B(3 downto 1);
end if;
if Sh = '1' then
A <= A(3) & A(3 downto 1);
B <= A(0) & B(3 downto 1);
end if;
end if;
end process datapath;


F <= A(2 downto 0) & B;
E <= X;
end BEHAVE;