sameer_ciit
Newbie level 1
Hello,
I want to use FIFO component in vhdl. I have successfully designed FIFO component and it is working fine, i have tested it with testbench. But the problem is i don't know how to use this component in vhdl code.
Here is description of work i want to do. I have another component named ALU, one instantiation of it will write data into FIFO(PUSH) and other will read data from FIFO(POP). The code is
May be this is basic question but as i am new to VHDL, so i can't understand how to solve it. I will be thankful to you for your help.
I want to use FIFO component in vhdl. I have successfully designed FIFO component and it is working fine, i have tested it with testbench. But the problem is i don't know how to use this component in vhdl code.
Here is description of work i want to do. I have another component named ALU, one instantiation of it will write data into FIFO(PUSH) and other will read data from FIFO(POP). The code is
Code:
[b]library ieee;
use ieee.std_logic_1164.all;
entity exam3 is
generic ( B: natural:=8; -- number of data bits
W: natural:=2 -- number of address bits
);
port(v10: in std_logic_vector(7 downto 0);
clk: in std_logic;
v40: out std_logic_vector(7 downto 0));
end exam3;
architecture structure of exam3 is
component alu is
port(a,b:in std_logic_vector(7 downto 0);
clk:in std_logic;
sel:in std_logic_vector(2 downto 0) ;
c: out std_logic_vector(7 downto 0));
end component;
component fifo
generic (B : natural;W:natural);
port ( clk: in std_logic;
rd, wr: in std_logic;
w_data: in std_logic_vector ( B-1 downto 0) ;
empty, full: out std_logic ;
r_data : out std_logic_vector ( B-1 downto 0));
end component;
signal rd,wr,s_empty,s_full: std_logic;
signal v4,v5: std_logic_vector(7 downto 0);
begin
u3: alu port map(v10, v5,clk,"101",v40); --xor
u_fifo:fifo
generic map(B=>B,W=>W)
port map(clk=>clk,rd=>rd,wr=>wr,
w_data=>v4,empty=>s_empty,full=>s_full,r_data=>v5);
u2: alu port map(v10, "11111111",clk,"001",v4); --and
end structure;
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