how to use EPC1010 SPICE model in Orcad PSPICE

[ronny2005]

Please help me to change the EPC1010 spice model to use in orcad lite 16.6
The file is here thanks
https://epc-co.com/epc/documents/spice-files/PSPICE/EPC1010_V101_PSPICE.net

 

[dick_freebird]

It should be good-to-go, just use the X subcircuit call and
embed / include the subcircuit definition.

Unless youe "lite" version is severly limited, like not digesting
some of the syntax or something. But EPC made you a PSPICE
model according to the header, so what's the problem?

 

[ronny2005]

It should be good-to-go, just use the X subcircuit call and
embed / include the subcircuit definition.

Unless youe "lite" version is severly limited, like not digesting
some of the syntax or something. But EPC made you a PSPICE
model according to the header, so what's the problem?

i am newbee. I dont knowhow to change this file to lib file. i only know to changelib to olb using model editer. please help by converting the file to lib. thanks sir for response.

 

[mvaseem]

What you have is a spice subckt for EPC1010.
You need to instantiate this subckt in your own ckt providing stimulus/load on the terminals.

I tried to build simple ckt around this, which simulates successfully in Pspice Lite.
I am doing DC sweep (drain voltage) at gate voltage=3V.
The drain current matches exactly with the datasheet.

Attached file is with extension '.txt' (eps.txt). Change extension to '.cir' (eps.cir).
In Pspice do File->Open Simulation. Change the File Type to .cir. Browse for the file and simulate.

 

[ronny2005]

Thanks mvaseem for the response, my problem is, i need to use it in Orcad lite so i need LIB file. Please help me converting the text file to lib file. or i dont know to use this file in my Orcad 16.6 lite schematic , please guide me step by step.

 

[mvaseem]

Do you already have schematic with this part instantiated ?
Then you just need lib file. Just copy the content in notepad and save as a lib file (say - eps.lib). Now provide the lib file in simulation settings by following steps -
Go to - Simulation -> Edit Settings -> Congiguration Files (Tab) -> Category- Library -> Browse for the lib file. -> Add to Design.

You are all set to simulate the model.

 

[ronny2005]

Do you already have schematic with this part instantiated ?
Then you just need lib file. Just copy the content in notepad and save as a lib file (say - eps.lib). Now provide the lib file in simulation settings by following steps -
Go to - Simulation -> Edit Settings -> Congiguration Files (Tab) -> Category- Library -> Browse for the lib file. -> Add to Design.

You are all set to simulate the model.

Thanks mvaseem once again, i saved the file as lib -> created olb too using model editor-> made schematic of the part epc1010->then Simulation -> Edit Settings -> Congiguration Files (Tab) -> Category- Library -> Browse for the lib file. -> Add to Design

But the simulation gives error -> string too long
and after breaking the long lines to short lines using + sign, it gives error message -> invalid number and invalid
Please help.

 

[mvaseem]

Are you able to simulate the cir file I attached in my first post. Just follow the steps mentioned. I could simulate that at my end with 16.6 Lite version. If you can simulate it without error, it would be easy to find the root cause of your problem.

 

[ronny2005]

yeah, I can simulate it without error

 

[ronny2005]

now i am getting following error. please help


**** 08/14/14 20:44:30 ****** PSpice Lite (October 2012) ****** ID# 10813 ****

 ** Profile: "SCHEMATIC1-e"  [ E:\thesis pspice\1\class e-pspicefiles\schematic1\e.sim ] 


 ****     CIRCUIT DESCRIPTION


******************************************************************************




** Creating circuit file "e.cir" 
** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY SUBSEQUENT SIMULATIONS

*Libraries: 
* Profile Libraries :
.INC "E:\thesis pspice\1\class e-pspicefiles\schematic1\e\e_profile.inc" 
* Local Libraries :

**** INCLUDING e_profile.inc ****
.INC    ".\eps.lib" 

**** INCLUDING eps.lib ****
*
X1 g d s EPC1010 
V1 g 0 3V
V2 d 0 1V
R1 s 0 1m
.DC LIN V2 0 2 0.1 
.probe
* source EPC1010DEV1
*$
.subckt EPC1010 gatein drainin sourcein
.param aWg=599  k1=28 k2=1.85 k4=1 
+       ags1=4.06e-10 ags2=4.69e-10 ags3=4.28e-12 ags4=1.25 ags5=.156 
+       agd1=3.15e-11  agd2=1.24e-10 agd3=-1.95 agd4=4.01 agd5=.022e-12
+       asd1=130E-12 asd2=300E-12 asd3=-100 asd4=60 asd5=180E-12 asd6=-15 asd7=3.0
+       dgs1=4.3e-7 dgs2=2.6e-13 dgs3=.8 dgs4=.23  
+       aITc=.0025 aSTc=.0005
rd drainin drain .0057
rs source sourcein .0001
rg gatein gate {(.6*1077/aWg)}
*Large resistors to aid convergence
Rcsdconv drain source {100000Meg/aWg}
Rcgsconv gate source {100000Meg/aWg}
Rcgdconv gate drain {100000Meg/aWg}
gswitch drain source Value {if( v(drain,source)>0.0,
+       ((1-aITc*(Temp-25))*k1*ags5*log(1.0+exp((v(gate,source)-k2)/ags5))*(1-exp(-(k4*(1-aSTc*(Temp-25)))*v(drain,source)))),
+       (-1*(1-aITc*(Temp-25))*k1*ags5*log(1.0+exp((v(gate,drain)-k2)/ags5))*(1-exp(-(k4*(1-aSTc*(Temp-25)))*v(source,drain))))
+        )}
ggsdiode gate source VALUE {if( v(gate,source) < 10,
+       0.5*aWg/1077*(dgs1*(exp((v(gate,source))/dgs3)-1)+dgs2*(exp((v(gate,source))/dgs4)-1)),
+       0.5*aWg/1077*(dgs1*(exp((10)/dgs3)-1)+dgs2*(exp((10)/dgs4)-1)) ) }
ggddiode gate drain Value {if( v(gate,drain) < 10,
+       0.5*aWg/1077*(dgs1*(exp((v(gate,drain))/dgs3)-1)+dgs2*(exp((v(gate,drain))/dgs4)-1)),
+       0.5*aWg/1077*(dgs1*(exp((10)/dgs3)-1)+dgs2*(exp((10)/dgs4)-1)) ) }
*Parasitic gate-source capacitance
*C_GS         gate source  {ags1}
*Model for voltage dependent gate-source capacitance
E_IGS tl_gs bl_gs value = {ags2*ags5*log(1.0 + exp( (v(gate,source)-ags4)/ags5 ) )+ 
+       ags1*v(gate,source) + ags3*0.5*v(gate,source)*v(gate,source)}
V_INGS br_gs bl_gs 0.0
C_IGS br_gs tr_gs {1.0e-6}
R_IGS tr_gs tl_gs {1.0e-4}
F_IGS gate source V_INGS 1e6
R_IGS2 bl_gs source 100Meg
*Parasitic gate-drain capacitance 
*C_GD         gate drain  {agd1}
*Model for voltage dependent gate-drain capacitance
E_IGD tl_gd bl_gd value = {agd2*agd4*log(1.0 + exp( (v(gate,drain)-agd3)/agd4 ) )+ 
+       agd1*v(gate,drain) + agd5*0.5*v(gate,drain)*v(gate,drain) }
V_INGD br_gd bl_gd 0.0
C_IGD br_gd tr_gd {1.0e-6}
R_IGD tr_gd tl_gd {1.0e-4}
F_IGD gate drain V_INGD 1e6
R_IGD2 bl_gd drain 100Meg
*Parasitic source-drain capacitance 
*C_SD         source drain  {asd1}
*Model for voltage dependent source-drain capacitance
E_ISD tl_sd bl_sd value = {asd2*asd4*log(1 + exp( (v(source,drain)-asd3)/asd4) ) + 
+       asd5*asd7*log( 1 + exp((v(source,drain)-asd6)/asd7)  ) +
+       asd1*v(source,drain) }
V_INSD br_sd bl_sd 0.0
C_ISD br_sd tr_sd {1.0E-6}
R_ISD tr_sd tl_sd {1.0e-4}
F_ISD source drain V_INSD 1e6
R_ISD2 bl_sd drain 100Meg
.ends
*$

**** RESUMING e_profile.inc ****

**** RESUMING e.cir ****
.LIB "C:/OrCAD/OrCAD_16.6_Lite/tools/pspice/library/eps.lib" 
* From [PSPICE NETLIST] section of C:\SPB_Data\cdssetup\OrCAD_PSpice/16.6.0/PSpice.ini file:
.lib "nomd.lib" 

*Analysis directives: 
.TRAN  0 1us 0 .00001u 
.OPTIONS ADVCONV
.PROBE64 V(*) I(*) W(*) D(*) NOISE(*) 
.INC "..\SCHEMATIC1.net" 



**** INCLUDING SCHEMATIC1.net ****
* source CLASS E
V_V1         VIN 0  
+PULSE 10 0 0 10n 10n 2.5e-7 5e-7
R_R1         VIN N01566  4  
R_R3         VO N01485  10  
L_L1         N01485 N01780  100uH  
V_V2         0 N01780 5Vdc
X_U1         N01566 VO 0 EPC1010

**** RESUMING e.cir ****
.END

INTERNAL ERROR -- Overflow in device X_U1.gswitch, Convert

ABORTING SIMULATION
**** 08/14/14 20:44:30 ****** PSpice Lite (October 2012) ****** ID# 10813 ****

 ** Profile: "SCHEMATIC1-e"  [ E:\thesis pspice\1\class e-pspicefiles\schematic1\e.sim ] 


 ****     JOB STATISTICS SUMMARY


******************************************************************************



Node counts:
  Top level (NUNODS)                =           9
  External (NCNODS)                 =          39
  Total (NUMNOD)                    =          39

Total device count (NUMEL)          =          63
  Capacitors (C)                    =           6
  VCVS (E)                          =           6
  CCCS (F)                          =           6
  VCCS (G)                          =           6
  Inductors (L)                     =           1
  Resistors (R)                     =          27
  Voltage Sources (V)               =          10

Number of subcircuits (X)           =           2

Matrix statistics:
  Matrix size (NSTOP)               =          56
  Initial no. elements (NTTAR)      =         184
  No. elements w/ fillin (NTTBR)    =         256
  No. fillins (IFILL)               =          72
  No. overflows (NTTOV)             =         148
  No. LU operations (IOPS)          =        1957
  Percent sparsity (PERSPA)         =      91.837

Analysis statistics:
  No. total time points (NUMTTP)    =           0
  No. rejected time points (NUMRTP) =           0
  No. iterations (NUMNIT)           =           0

Load Threads                        =           1

Runtime statistics:                       Seconds      Iterations
  Matrix load                       =        0.00
  Matrix solution                   =        0.00               2
  Readin                            =         .02
  General setup                     =        0.00
  Setup                             =        0.00
  DC sweep                          =        0.00               0
  Bias point                        =        0.00               0
  AC and noise                      =        0.00               0
  Total transient analysis          =        0.00
  Output                            =        0.00
  Overhead                          =        0.00
  Total job time (using Solver 1)   =         .02


 

[mvaseem]

You are getting overflow in device "gswitch" (used in model epc1010), during bias point callculation. Overflow typically means the expression in gswitch is returning exceptionally high values by virtue of exponentials used or getting the denominators very low. I tried your ckt with following settings to simulate it successfully.
1) using skipbp (skip the bias point calculation) and directly run transient.
2) using cshunt=100f (available in options->advanced options). Cshunt would add virtual capacitance to each node in your design to smoothen spikes. This would however change the design topology and the output results need to be verified by intuitive analysis.

You can play with other advanced options to get it converged.

Also you seem to have added epc.lib twice in your simulation profile. Remove one of them. Use the one available on website.