Well, it depends how much delay you would like. In a synthesizeable design its not possible to have a definite delay inserted when the delay value is less than 1/2 the clock period of the clock you are using. Using buffers will give you a delay, but the delay value will not be deterministic. Well, if you would like to have a delay of more than 1/2 a clock period, then you can use a counter to implement that, or if the delay is just 1 or 2 clock periods, then just pass the signal throuth 1 or 2 D flip flops respectively. Hope it helps,
kr,
Avi