How to use D Latch in RTL

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dhanya22

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Hello

Is it possible to use a D Latch i mean LD in design using VHDL ?
Because I always see FD in RTL and never LD.But I need a LD , how is it possible to use ?
 

If you mean that you don't often see latches in RTL that is targeting fpga's, then that is probably because for fpga's latches are generally a bad idea. Static timing analysis and all that.

Do you want to use latches in an fpga design? If yes, then why?

- - - Updated - - -

Also, if you want latches, just use an incomplete case statement. You'll have your latches in no time. XD
 

Code: 
reg crpy_latch;
always @* begin
  if (enable) begin
    crpy_latch <= din;
  end
end

//or
wire crpy_latch;
assign crpy_latch = enable ? din : crpy_latch;

There now you have a crummy latch in your design...good luck with it.
 

I am trying to make a master slave D Flip flop for that I want a master Latch and Slave Latch(i.e D latch) with two inverters.
Now I am able to use the latches, I used the following:

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entity Latch is
    Port ( D : in  STD_LOGIC;
           G : in  STD_LOGIC;
           Q : out  STD_LOGIC);
end Latch;


architecture Behavioral of Latch is

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begin
process(G,D)
  begin
   if (G='1') then
     Q <= D;
    end if;
end process;
     end Behavioral;


So the problem is solved
Now a new problem has arised , I am using two inverters which are driven by Clock, but I only see one inverter in technology schematic.Can anybody help me in that
 
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Why do you need 2 inverters? All the schematics I am aware of use only a single inverter..
 

Because I am using a master slave D Flip Flop, which is made using two D latches and two inverters.
What I am doing is this:
I am driving first latch through first inverter from clock, and second latch through the second inverter.
I am able to see the two inverters in RTL, but when I see the technology schematic i see only a single inverter
 

Are you sure you aren't see some sort of NOT gate push back/forward?

Try running a netlist simulation on the synthesis results.
 

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