How to use cpld as eeprom as non v0latile memory ?

[Lokesh Waran]

Dear friends ,

I want to store some data in to the CPLD -XC9572 Series device as non volatile information for the purpose of read that data when i need to receive that bits .Bec in my knowledge CPLD is the EPROM Technology basis ,So any one can clarify this doubt ??????????????????????????????? i am tried to store the data using verilog HDL coding below but the data which i have written in to the device is lost after switch of the device power sourse. thanking you for your information if u post answer for this drawback.

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Code Verilog - [expand]
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module eeprom (
address , // Address input
data    , // Data output
read_en , // Read Enable 
ce      , // Chip Enable
oe      ,
out     ,
write_en    
);
input [2:0] address;
input [2:0] data; 
output out;
input read_en; 
input  write_en; 
input ce;
input oe; 
           
reg [2:0] mem [0:6] ; 
reg  out=0 ; 
 
always @( read_en or ce or write_en or oe or address or data)
begin 
 
if ( ce &&  write_en)  
    mem[address]<= data;
     
 
if (oe && read_en)
    out <= mem [address];  
   
 
end 
 
endmodule

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[bigdogguru]

While the design implementation programmed into the CPLD is nonvolatile, this by no meanings implies any data stored into the memory implementation is nonvolatile.

Data stored within the an implementation of RAM memory is volatile, regardless of whether the actual design implementation programmed into the device, CPLD or FPGA, is volatile or nonvolatile.

BigDog

 

[aruipksni]

While the design implementation programmed into the CPLD is nonvolatile, this by no meanings implies any data stored into the memory implementation is nonvolatile.

Data stored within the an implementation of RAM memory is volatile, regardless of whether the actual design implementation programmed into the device, CPLD or FPGA, is volatile or nonvolatile.

BigDog

i guess the way to do it is via jtag, then it can be used as a jpag eeprom.
so you will need to implement the jtag controller with a cpu.