you can declare a pin as inout and try it.
I suppose you have to place the three-state buffer between the transmitter and the line itself. When you are about to receive, you merely disconnect the transmitter by forcing it's output to 'Z'. The receiver doesn't need this, it would be always connected.
Correct me if I'm wrong, please.
module i2cwrite(
input rst,
input clk,
input [7:0] data,
output scl,
??? sda
)
//body here
endmodule
inout sda
sda <= 1'bz; //put sda in high impedance mode
Yes, something like that. I don't quite remember Verilog, but I think there is "inout" port direction specifier.The current module declaration is something like this
do I need to do something like this
Code:inout sda
to make sda bidirectional?
Yes. In a transmitter module.Once I make it bidirectional how to set it as input?
will something like this make it an input?
Code:sda <= 1'bz; //put sda in high impedance mode
I'm gonna need to search the Internet. Like I said, don't remember Verilog. Obviously, you need to declare this line as a net, but I don't remember the exact syntax.When I do something like
"inout sda"
The hdl compiler flags an error saying cannot
"Non-net port sda cannot be of mode inout"
Any idea why this error is occurring?
You can read the line anytime you want. Just connect it to the input of your module and do what you want to do.Another point is I want to make "sda" as an input so that I can read the data sent by the data sent by the slave on the same line. By I haven't any clue of how to read the sda into a reg inside the FPGA?
Means the pin is not connected correctly in the design."Non-net port sda cannot be of mode inout"
by an assignment, e.g. xx <= sdahow to read the sda into a reg inside the FPGA?
You are talking now about basic Verilog syntax issues rather than I2C related questions.
Means the pin is not connected correctly in the design.
Post the code of your module
module i2cwrite(
input rst,
input clk,
input [7:0] data,
output scl,
output sda
)
reg sda;
reg scl;
//other variables
//body here
endmodule
Because it's "reg". Should be wire.
sda has to assigned primarly by a conditional assignment, something likeAfter changing
"reg sda" to "wire sda"
I get errors
assign sda = (sda_reg)?1'b0:1'bz;
Your port declaration style is somewhat unusual, ether all, or no parameters of each pin are expected to be defined in the port list.
As I was taught in the university, there are two styles of Verilog module declaration: an "old" one and a "new" one. They differ by the style of ports declaration. As far as I know, both types are supported by most, if not all, modern compilers.Your port declaration style is somewhat unusual, ether all, or no parameters of each pin are expected to be defined in the port list.
output reg scl,
output reg sda
As I was taught in the university, there are two styles of Verilog module declaration: an "old" one and a "new" one. They differ by the style of ports declaration. As far as I know, both types are supported by most, if not all, modern compilers.
Your style is corresponding to neither of them.
Hm, you are right. Apparently, some compilers allow mixing...Your style is corresponding to neither of them. According to the "new" style, the reg goes into the port declaration list.
Code:output reg scl, output reg sda
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