How to use available models in VHDL-AMS

[abhaykochhar2]

hi all. how can we use available models in VHDL-AMS.. as this facility is available in MAST.. is the same facility available in VHDL-AMS??

waiting for ur replies..

regards...
ASCII

 

[Blackuni]

Hi Abhay,

I don't think vhdl ams is supported by synopsys.

u can do it with verilogA silvaco provides it open. If u get it please help me with it.

Thanks

 

[abhaykochhar2]

synopsys does support vhdl-ams.. DISCOVERY AMS is by synopsys only.. but can we use our model files for further designing??

 

[Blackuni]

Hi,

are u saying that u can use model written in vhdl-ams(device models) in Synopsys Discovery AMS tools?

is so..

Please go through docs of tools avaliable in dicov. ams.

Then u will accept

Thanks

 

[abhaykochhar2]

yes its true.. Discovery AMS is for this vhdl-ams only..
try www.synopsys.com/products...

or simply u write ur code in .va format.. and u can simulate using HSPICE..
HSPICE simulates verilog A format files...
try it out.. let me know also.. i m also started now only..
i m beginner in this .. so if m wrong newhere please correct me...
thanks..
regards
abhay

 

[Blackuni]

Hi,

That is not vhdl AMS it is verilog AMS

Thnks