how to use Analog Env. to simulate verilogA

[nijMcnij]

how to simulate veriloga in cadence schematic

hello all,

can someone please tell me how to use cadence analog enviroment (spectre) to simulate mixed signal models described in verilogA.

many thanks

 

[eng_Semi]

generate symbol veriloga

If ur design has more than one view (schematic, av_extracted, veriloga, ... etc) use the config view (hierarchy editor) to chosse which view to simulate with. Then simulate as usual.

 

[safwatonline]

comparator veriloga model

If ur design has more than one view (schematic, av_extracted, veriloga, ... etc) use the config view (hierarchy editor) to chosse which view to simulate with. Then simulate as usual.

hello semi,
i am using cadance , when i try to make simulation i create a new cell for each design level (schematic , verilog ,etc..) can i add these different level of cells under one cell and during simulation i could choose which level to simulate ?
thnx and regards.
a.safwat

 

[yaxazaa]

vpwl veriloga

After edit the verilogA file, generate a symbol. Instantiate in the another schematic view. After this, it will be the same as other simulation in Analog Artist.

 

[Hughes]

using vpulse in veriloga

You can simulate the verilogA by the way just as yaxazaa mentioned. If you have multiple views for the same cell, you may use "switch view list" to choose which view to use. Set the "switch view" in the "Set envirionment" form. To use veriloga view, put veriloga before other views (such schematic view).

 

[nijMcnij]

veriloga if

thank you all for your helpful comments,

i am trying to simulate the system behaviour of a charge redisrtibution SAR ADC, i have created the modules for the comparator, capacitors, switches and control logic in verilogA, and then i created the symbols as pointed out in the comments, what remains now is to connect the entire system in a single schematic and then run the simulation....that is what i didn't figure out yet.

1-how do add a sin wave source with a specific frequency and amplitude?...i know of this function vsource(), but can i add vsource or vsin from the library manager?

2-how do i set up the ac simulation (ac, dc,transient, or what have u)...can i use the analog environment and just click choose analysis--->dc ?

3-how do i plot the outputs and see waveforms?

many thanks

 

[Hughes]

analog environment ac simulation

Suppose you want simulate your SAR ADC in transistor level. You create the schematic views for the comparator, switches and other parts. You also create symbol views for these sub-circuits. You create the top-most schematic view of the SAR ADC (named SARADC), using symbol views of comparator, switchs and other parts. Then you add vsin, vpwl, vpulse (from analogLib) to SARADC/schemetic. Then you can simulate the desing using the ADE.

Simulating with verilogA is just like the above case. You create the veriloga view of the comparator. If the symbol view doesn't exist, you will be prompted to create one. You can optionally modify the symbol. You create veriloga views and symbol views of capacitors, switches, and other parts in the same way. The top-most schematic view of the SAR ADC may be the same with the above case, because in a hierarchy design, you usually use symbol views rather than schematic to call sub-circuits. Therefore, the simulation procedure is the same. You add vsin, vpulse, vpwl instances to the top-most schematic. Then you use ADE to simulation the design add view waveform just like in full-schematic example. The only difference is you should put "veriloga" before "schematic" in the "switch view list" if any sub-circuit has both a schematic view and a veriloga view.