analog environment ac simulation
Suppose you want simulate your SAR ADC in transistor level. You create the schematic views for the comparator, switches and other parts. You also create symbol views for these sub-circuits. You create the top-most schematic view of the SAR ADC (named SARADC), using symbol views of comparator, switchs and other parts. Then you add vsin, vpwl, vpulse (from analogLib) to SARADC/schemetic. Then you can simulate the desing using the ADE.
Simulating with verilogA is just like the above case. You create the veriloga view of the comparator. If the symbol view doesn't exist, you will be prompted to create one. You can optionally modify the symbol. You create veriloga views and symbol views of capacitors, switches, and other parts in the same way. The top-most schematic view of the SAR ADC may be the same with the above case, because in a hierarchy design, you usually use symbol views rather than schematic to call sub-circuits. Therefore, the simulation procedure is the same. You add vsin, vpulse, vpwl instances to the top-most schematic. Then you use ADE to simulation the design add view waveform just like in full-schematic example. The only difference is you should put "veriloga" before "schematic" in the "switch view list" if any sub-circuit has both a schematic view and a veriloga view.