Hi All, I have a input with a specific duty cycle, for example, varying from 40% to 80% and cycle is 100kHz. I tried to use this input to generate an output using the duty cycle information. The detailed in attached, could anyone advise how to implement the process circuit? Thank you very much!
Hi Jinzpaul4u, thank you for the files. I just want to use some digital logic circuits (AND, OR, timer, etc) to implement this function. What I want is to extract the first duty cycle from a PWM signal (maybe reset after several cycles, but we can ignore this at this moment), and make the length of this to be 50% of output cycle.
For example, I have a input with 100kHz, so one cycle is 10uS. And the duty cycle is 10%, so we have 1uS high per cycle. What I want is to use this 1uS to generate a 2uS clk signal and its duty cycle is 50%. Similarly, if I have 20% duty cycle of input signal, I have 2uS high per cycle in the input, and I want output to be a 4uS clk signal.
I read your files but still not clear if they can be used to achieve what I want, could you give me more advise? Thank you!
Can be hardly solved without a complex digital circuit, involving a clock generator, a pulse width measuring counter, a programmable timer to reproduce the period, a sequence controller.
I believe you are talking about a duty-cycle to frequency converter. I agree with FvM. It sounds like a rather complex task.
If some inaccuracy can be tolerated you could perhaps average the variable-duty cycle signal to get a varying DC voltage and use the to control a voltage-controlled-oscillator (VCO).
Can be hardly solved without a complex digital circuit, involving a clock generator, a pulse width measuring counter, a programmable timer to reproduce the period, a sequence controller.