bravoegg
Member level 2
I want to download bit to FLASH, not by JTAG, but by user logic. I now have one possible idea in mind:
Because CCLK is a dedicated pin, user logic cannot use it(I know by primitive it can still be used, but not now). Instead use a common-purpose IO, define it as a SPI_CLK output to FLASH.
In this method, there're actually two FPGA ports connected to the FLASH's clock port, one is the CCLK which is active during configuration, the other is SPI_CLK defined by user logic. Both CCLK and SPI_CLK are up-pulled.
The other spi related pins, such as sdi, sdo, chip_select, are multi-purpose pins which could be used later by user logic, so no need to define another set of pins.
I tend to think it'll work but not sure. Could someone assure me of that?:|
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Or is it more sensible to leave the schematic just as a typical SPI configuration. No extra pins defined or connected.
After FPGA configuration, use primitive STARTUPE2 to utilize CCLK, the other MOSI MISO CE pins could be reused directly by user logic.
Because CCLK is a dedicated pin, user logic cannot use it(I know by primitive it can still be used, but not now). Instead use a common-purpose IO, define it as a SPI_CLK output to FLASH.
In this method, there're actually two FPGA ports connected to the FLASH's clock port, one is the CCLK which is active during configuration, the other is SPI_CLK defined by user logic. Both CCLK and SPI_CLK are up-pulled.
The other spi related pins, such as sdi, sdo, chip_select, are multi-purpose pins which could be used later by user logic, so no need to define another set of pins.
I tend to think it'll work but not sure. Could someone assure me of that?:|
- - - Updated - - -
Or is it more sensible to leave the schematic just as a typical SPI configuration. No extra pins defined or connected.
After FPGA configuration, use primitive STARTUPE2 to utilize CCLK, the other MOSI MISO CE pins could be reused directly by user logic.