How to temporarily reduce the supply voltage level of an SRAM cell in HSPICE?

[kilian86]

Hello,
I am new to HSPICE simulations and might need a bit of your help.
I have a simple 6T SRAM cell and I would like to reduce its supply voltage VDD for a short period of time (a voltage source). I expect the cell node Q and QB to flip after pulling the voltage supply to zero or at least to react accordingly, however they do not. What is wrong with my HSPICE set up? Does anyone have an idea? Thank you so much for helping me.
Kilian

The code I use is as follows:

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Code PHP (brief) - [expand]
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** ground **
V_VSS VSS 0 DC 0                                                   
** wordline voltage **
V_WL WL 0 DC 0
** BL voltage **                                                          
V_BL BL 0 DC 0
** BLB voltage **                                                             
V_BLB BLB 0 DC 0  
 
** supply voltage **
V_VDD VDD 0 PWL('0n' 2 '5n' 2 '5.1n' 0 '15n' 0 '15.1n' 2)       
                                                          
 
.IC V(Q) = 2
.IC V(QB) = 0
 
** pull down devices **
X_PD1 QB Q VSS VSS NMOS L=0.5U W=0.1U 
X_PD2 Q QB VSS VSS NMOS L=0.5U W=0.1U 
 
** access devices **
X_A1 V_BLB V_WL QB VSS NMOS L=0.5U W=0.8U 
X_A2 Q V_WL V_BL VSS NMOS L=0.5U W=0.8U 
 
** pull up devices **
X_PU1 QB Q VDD VDD  PMOS L=0.5U W=0.5U 
X_PU2 Q QB VDD VDD  PMOS L=0.5U W=0.5U
 
 
.OPTION POST
.TRAN 10p 100n

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[erikl]

I expect the cell node Q and QB to flip after pulling the voltage supply to zero ...

Why should they flip? Static RAM is expected to keep its state without power supply. That's what it is intended for, isn't it?

 

[kilian86]

Why should they flip? Static RAM is expected to keep its state without power supply. That's what it is intended for, isn't it?

Well, maybe the word static is a bit misleading here. A SRAM cell consists of two CMOS inverters and two access transistors and will definitely lose its state when it is not powered. The standard SRAM is a volatile memory type.