Normally by using 'wait states'. Something in the circuit (the memory address decoder perhaps) either controls the CPU clock speed so it drops when a slow device is selected or it tells the CPU to execute 'no operation' instructions to allow time for the slow device to respond. It depends on whether the CPU supports wait states, some do, some don't.
The interrupt depend on whether it is edge or level detected. If the CPU uses edge detection it may be necessary to externally sync the interrupt signal with the slow device or even use the wait/slow clock method of processing it.
So really, the answer to both questions is it is very dependant on the CPU type.
Brian.