Does anyone have any idea how to synthesize a generated clock?.
What i have is CLK2 and CLK1.
Clk1 is global clock.
Clk2 is generated using CMOS logic. Inputs of this CMOS logic comes from gates that use CLK1 as their clock.
What I am trying to build is a self timed circuit. Level-2 waits for Level-1 to complete. CMOS logic in between behaves like a clock generator for level2.
I will be really appreciate if you can give me some idea how to
synthesize this in Cadence RTL complier or in DC with commands that can be feed to RTL complier.
Re: How to synthesize generated clock in cadence RTL complie
Hello srpatel9,
Could you elaborate ur design, means how u are generating the clock ?
How u re using it.(any diagram ?)
As much i can understand from ur description, u can create generated clock in ur constraints for synthesis.
Even if you do not define generated clock, i think ur circuit will be synthesised.
1) How tool understands the clk2 is a clock signal ?
For this, u have to define generated clock constraint(and feed this constraint to synthesis tool) at the place where clk2 is generated. Then for rest of the hardware clk2 will be treated as clock signal by tool.
:IN SDC format command is: "create_generated_clock". In you tool help(Design Compiler) u will can all information about this command.
2) Regarding encounter: Encounter or any backend tools needs constraints file with netlist. This constraint file typically is sdc file. In this file u will be having the generated clock defination. In generated clock defination u can also define edge relationship of generated clock with source clock.
I hope this answers ur questions :!:
Added after 13 minutes:
In RTLCompiler use the command "read_sdc" for reading your SDC constraints.