Hi
I've got a clock divider circuit based on flip-flops and I'm doing corner simulations with Hspice. The problem is that the same clock signal is different depending on the corner because of the initial value at the input of the flip-flops. I mean, the same clock signal is 180º delayed in some cornes.
How can I achieve clock signals to be synchronized?
Thanks
Hi
I've got a clock divider circuit based on flip-flops and I'm doing corner simulations with Hspice. The problem is that the same clock signal is different depending on the corner because of the initial value at the input of the flip-flops. I mean, the same clock signal is 180º delayed in some cornes.
How can I achieve clock signals to be synchronized?
Thanks
Well, in case you want the clock divider circuit to function in the same way, you can delay the input clock for a while till the JK(or T inputs) settle. Hence the initial conditions are maintained.
Just explain why you want your output signal to be sysncronized among diferent corner simulations. If you want to perform measurements on the output signals, use the extract capabilities of your simulator
You must have a reset control pin in your clock divider circuit so that all D-flipflops always has the initial states that under your control. Initial condition set by simulators is not trustable in such type of circuits.
Another method is to use some kind of self-starting clock divider, so that no matter what the initial state the clock divider can work properly.
Attach .IC command to some node. It may be parametrized, such as
.IC V(nXXX)='VDD' V(nYYY)=0
.ALTER Slow
.PARAM VDD = '0.9*Vdd'
.Temp XXX
>LIB 'XXXX'
.ALTER Fast
.......