To suppress the distortion of the sampling switches that needed to pass 500MHz bandwidth signal, some techniques has been done it before:
1) Increase the transistor size to reduce the on resistance, so that the distortion is suppressed. However, a big transistor also makes a bit parasitic capacitor. I tried this technique, the transmission gate transistors size turns out to be W/L=2700! to keep the THD as low as 0.1% at 500MHz. This size is ridiculous.
2) Bootstrapping technique, which keep the Vgs of the transistor constant when the switch turns on. Compare to technique 1), it only requires W/L=300 to keep the THD as low as 0.001%. However, this technique requires complicated layout. I been told that the guy who first pulish this technique spent one year on the layout!
3) Peoples saying that connect the source of the p-type transimission switches to the bulk(body) when the switch is on (on-resistance reduced), then connect it back to vdd when it is off (off-resistance increased). However, the distortion performance does not improved when I do the simulation in spice.
Does anyone have any advice regarding to this topic? Any suggestion would be greatly appreciated.
Thanks for the reply. I did use the bottom plate sampling and is in a fully differential architecture. However, when I simulate the THD in spice, the transimission switches are held on, and the bottom plate switches is tied to a common mode voltage. Since the switches are not switching, does it matter to the THD standpoint?
Thanks for the reply. I did use the bottom plate sampling and is in a fully differential architecture. However, when I simulate the THD in spice, the transimission switches are held on, and the bottom plate switches is tied to a common mode voltage. Since the switches are not switching, does it matter to the THD standpoint?
I think bootstrap is ok. Layout is not a fatal problem as it is mature techs right now.
However distortion of SC sampling is not only contributed by the parasitic r, c during the switches "on" state, the MOS switches switching action may be more deadly and contribute more distortion.
Re: How to suppress distortion of the SC sampling switches?
One way to reduce distortion is to ensure that the switches deal with constant VGS. There are a lot of circuits for this purpose. People also use Clock Voltage doublers for less distortion
Another way is to use bootstrapping. I do not think that the layout for bootstrapping is very complicated.