Aug 5, 2011 #1 G girih192002 Full Member level 2 Joined Aug 4, 2007 Messages 130 Helped 19 Reputation 38 Reaction score 11 Trophy points 1,298 Location India Activity points 2,115 Hi, how to suppress charge injection effect in sample hold circuit ?
Aug 5, 2011 #2 D dick_freebird Advanced Member level 7 Joined Mar 4, 2008 Messages 8,988 Helped 2,333 Reputation 4,683 Reaction score 2,520 Trophy points 1,393 Location USA Activity points 71,586 You minimize the switch size (works against minimum sample time / settling) and/or inject a cancelling charge. But the charge required, will vary with common mode position if you use simple gate drives (like CMOS logic).
You minimize the switch size (works against minimum sample time / settling) and/or inject a cancelling charge. But the charge required, will vary with common mode position if you use simple gate drives (like CMOS logic).
Aug 6, 2011 #3 leo_o2 Advanced Member level 4 Joined Sep 3, 2004 Messages 1,322 Helped 278 Reputation 558 Reaction score 241 Trophy points 1,343 Location China Activity points 5,761 Add dummy transistors with appropriate size.