Hello,
i am "fighting" with a design where 2 32bit counters are generating data at diferent speeds.
The counters are enabled by a 1second gate signal, and on the falling edge of the signal, just when it reached 1s, i store the current counters values in a register for later usage (to be send on a uart module).
Each counter produces a 32bit value, in the end i have a 64bit value containing the two counters result, where i also add another 8bits containing a end header 8'h 0A.
So in total i have 72 bits
I have attached a simulation , where the red signal is the trigger and the blue one is the 64bit register
The code for this is bellow
Code:
module mux_64bit( trigger, data72_in, data72_hold,rdy);
input trigger;
input [71:0] data72_in;
output reg [71:0] data72_hold = 0;
output reg rdy=0;
reg [71:0] buffer =0;
always@(negedge trigger) begin
if(!trigger) begin
buffer<=data72_in;
data72_hold <= buffer;
rdy <=1'b1; // flag for "data ready"
end
else begin
buffer<=72'b0;
rdy <= 1'b0;
end
end
endmodule
And the top module instantiation
Code:
mux_72bit muxy(
.trigger(enable),// 1 second "store" signal
.data72_in({r32,s32,8'h0A}), // concatenate 2x32bits , plus a end header 0A
.data72_hold(data72),//output to a output reg of main module
.rdy(ready) // ready signal for uart module
);
So in simulation of course everything is working as expected, but when implemented on hardware... i have some random values inside the 64bit range, the 0A header is ok.
My question is, whats the practical aproach for such a procedure? Or how to safely store the data to be available between each cycle?
Thanks