1. Yes.. costs lot of $..
2. No you dont convert to systemc, which is not suitable for synthesis. you use Verilog/VHDL for synthesis. Before that you need to run a lot of simulations, in which systemc could help.
3. yes. synthesize after simulations are ok.
4. goes earlier than 3.
Get xilinx/altera software for synthesis if it's school project only. otherwise you pay five figures to Synopsys/Cadence to get a commercial synthesizer.
PT is for STA.
How come you knew a lot of keywords but misplace them in wrong places?
IP from ARM ,, will be having golden verilog files, you can directly start synthesizing ARM core,
am not in to Verification but am in to ARM implementation ,
you can use Reference methodology flow given by ARM
sorry if am wrong, my knowledge is limited to block level implementation (ARM cores)