How to split a power domain

[aditya1579]

Hi,

In my design, all memories belong to one power domain. But since they are spread all over the block, how do I split the power domain to place it wherever the memories are present ?

Thanks,
Aditya

 

[ThisIsNotSam]

memories usually require a completely different power distribution, so they do not resemble power domains we have for logic. You use a different VDD, different block rings, different core rings, different IO cells.

 

[riti]

memories usually require a completely different power distribution, so they do not resemble power domains we have for logic. You use a different VDD, different block rings, different core rings, different IO cells.

So we need to give two block rings/core rings in single die area. one for memory and another for std cells ?

 

[ThisIsNotSam]

usually that is a requirement, yes. but in complex SoCs, power domains get a little wild and you have to be more creative than that. things also change considerably whether your IO supports islands or if every IO cells has to be placed on the chip periphery.

 

[riti]

usually that is a requirement, yes. but in complex SoCs, power domains get a little wild and you have to be more creative than that. things also change considerably whether your IO supports islands or if every IO cells has to be placed on the chip periphery.

In complex SOC, as you mentioned we can do some creative thing. Could you please insight what creative we can do if our IO placed on chip periphery

 

[snaulh]

You should now the difference between power domain and voltage area. Power domain is logical definition and voltage area is physical one.
In your design, we have atleast 2 power domains, standard one for std area, one for placing-memory area. Each power domain maybe have more than one voltage area. Volatge area is an area we define on our design to declare where power domain should be implemented. In your case, you only need to define each volatge area where you placed memory.
More explaining about power planning for memory area is at #2