Nov 30, 2010 #1 A alekhyahetl Newbie level 3 Joined Oct 14, 2010 Messages 4 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,303 hi....i am new to verilog,i wanted to know what is inferred clk??????... i am getting warning like ( " Found inferred clock toplevel|clk with period 40.00ns. A user-defined clock should be declared on object "p:clk" ) can any one of you explain me about this.........
hi....i am new to verilog,i wanted to know what is inferred clk??????... i am getting warning like ( " Found inferred clock toplevel|clk with period 40.00ns. A user-defined clock should be declared on object "p:clk" ) can any one of you explain me about this.........
Apr 4, 2011 #2 D Dayn Newbie level 4 Joined Feb 16, 2011 Messages 5 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,315 alekhyahetl said: hi....i am new to verilog,i wanted to know what is inferred clk??????... i am getting warning like ( " Found inferred clock toplevel|clk with period 40.00ns. A user-defined clock should be declared on object "p:clk" ) can any one of you explain me about this......... Click to expand... I have the same error in VHDL design with Synplify Pro soft : Found inferred clock top|clk with period 10.00ns. A user-defined clock should be declared on object "p:clk" Did you fix your past error ? Best Regards, Dayn
alekhyahetl said: hi....i am new to verilog,i wanted to know what is inferred clk??????... i am getting warning like ( " Found inferred clock toplevel|clk with period 40.00ns. A user-defined clock should be declared on object "p:clk" ) can any one of you explain me about this......... Click to expand... I have the same error in VHDL design with Synplify Pro soft : Found inferred clock top|clk with period 10.00ns. A user-defined clock should be declared on object "p:clk" Did you fix your past error ? Best Regards, Dayn
Apr 8, 2011 #3 A alekhyahetl Newbie level 3 Joined Oct 14, 2010 Messages 4 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,303 hi dayn......... i didnt solve that problem...did u fix tht??????...if so please tell me
Apr 11, 2011 #4 zel Member level 5 Joined Apr 5, 2007 Messages 88 Helped 13 Reputation 26 Reaction score 12 Trophy points 1,288 Location Kuala Lumpur, Malaysia Activity points 1,714 i think it is not a problem..it is just a warning. and i think you design will be ok..its depends on how you design your design..
i think it is not a problem..it is just a warning. and i think you design will be ok..its depends on how you design your design..
Apr 18, 2011 #5 A alekhyahetl Newbie level 3 Joined Oct 14, 2010 Messages 4 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,303 ya....it is showing as a warning and there is no problem to the design,i wanted to know the reason, for that warning........can u explain me pls
ya....it is showing as a warning and there is no problem to the design,i wanted to know the reason, for that warning........can u explain me pls
Mar 12, 2012 #6 A alekhyahetl Newbie level 3 Joined Oct 14, 2010 Messages 4 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,303 Dayn said: I have the same error in VHDL design with Synplify Pro soft : Found inferred clock top|clk with period 10.00ns. A user-defined clock should be declared on object "p:clk" Did you fix your past error ? Best Regards, Dayn Click to expand... hi Dayn..... During synthesis assign a timing constraint for specified inferred clock......u can rectify from this. it is only defining the clock type(inferred,derived,declared and system).
Dayn said: I have the same error in VHDL design with Synplify Pro soft : Found inferred clock top|clk with period 10.00ns. A user-defined clock should be declared on object "p:clk" Did you fix your past error ? Best Regards, Dayn Click to expand... hi Dayn..... During synthesis assign a timing constraint for specified inferred clock......u can rectify from this. it is only defining the clock type(inferred,derived,declared and system).