Re: How to solve clock gating violations? even latch based doesnt seem to ignore gli?
Latch based clock gating
The latch-based clock gating style adds a level-sensitive latch to the design to hold the enable signal from the active edge of the clock until the inactive edge of the clock. Since the latch captures the state of the enable signal and holds it until the complete clock pulse has been generated, the enable signal need only be stable around the rising edge of the clock, just as in the traditional ungated design style.
Even the above method can introduce glitches, if you can check the timing diagrams clearly. So please help me if I am understanding the concept wrong.If possible someone prove that to me using timing diagrams.
help will be greatly appreciated.
Thanks
ARUN