How to solve both setup and hold violation without changing the clock paths

Status
Not open for further replies.
D

dynamicdude

Member level 2
Joined
Mar 15, 2005
Messages
47
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,286
Location
India
Activity points
1,855
Can anybody tell me how to react to both setup and hold violation in the circuit perspective without changing the clock paths?

If there are any relevant documents please let me know.
 

Re: Timing violation?

for hold time violations, we can add buffer before DFF's D input to increase

data delay; for setup time violation, the measure that we can take is

re-synthesis with more stringent constraints or re-code RTL code!


dynamicdude said:
Can anybody tell me how to react to both setup and hold violation in the circuit perspective without changing the clock paths?

If there are any relevant documents please let me know.
Click to expand...
 

Re: Timing violation?

hi
go thro your code to find any unuwanted combo logic infered and remove it.
pipelining your design can help
 
Reactions: pritis

    P

    pritis

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…