Hi, Skyhigh:
You are right, that the both methods are basically same. But I just feel that the a series ressitor won't make much difference, because here it is the slew current which decide the risetime in my case, thus a resistor will not
affest this slew current. That is what I think.
I also think that the risetime of 10% to 90% is about
2.2RC other than 0.63RC, .
I think for one feed path, I need about 12ns rise time to
avoid reflection, how do you think about this? The signal will come from a comparator or a flip-flop, go through a
coax cable, and a two-line I/O header, and then some
on-board trace until it reached the FPGA.
Why does a sample-hold circuit eliminate reflection and
transmission line circuit? While a sample-hold can be thought of a low-pass filter... What I can come up with is that a sample-and-hild will decrease the signal-changing rate, is that what you mean?
But a sample-and-hold makes my design complex which askes for a dedicated clock. But maybe it really addreses my problem.
SkyHigh said:
Hi greenfrog,
Both method 1 and 2 are about the same. Your cable is basically RLCG, with R and L dominating other electrical parameters with such a length like 1 ft long.
Method 1 - If you use a 1st order passive low-pass filter, it will be the similar to method 2. So you can have nth order passive or active filter. However the order here doesnt matter.
Method 2 - Adding a shunt capacitor is creating a 1st order passive low-pass filter or a series-shunt RC filter because your cable already has resistance.
From both methods you proposed, there is one thing in common, the shunt capacitance and series resistance. From any electronic design publications, one common way to reduce rise time or one common design problem that limits the rise time is shunt capacitance and series resistance.
The larger the shunt capacitance and series resistance, the longer the rise time because we know time constant = RC.
The formula for rise time (10% to 90%) is 0.63 RC.
Another method is to use a unity-gain buffer or voltage follower followed by a sample-hold circuit. Hence you can eliminate reflection and impedance mismatch on the transmission line (cable) and you can synchronise by means of a clock when you want to sample your signal from the buffer.