How to size a 4 GHz TSPC D-FF, 0.13um technology?

[ideal world]

hi every one

i am working on designing TSPC D-FF with 0.13 um technotogy at 4 GHZ

i don't know a proper way to size this D-FF

there is always a delay between the input and the output

more over when i use it in divide by 2 test bench the duty cycle is larger than 50%

that is my design and the results

i searched in rabaey for a good method but i couldn't find

please help me with that because i need it as soon as possible

thanks alot

 

[AdvaRes]

Re: TSPC sizing

Hi,

Input/output delay can be easily seen at 4 GHz. The only way to overcome that is to use minimum transistor sizes. I dont think also that there is a way to have a 50% duty cycle directly from the DFFs. My idea is to use a simple clock adjuster that ANDs the Clock with itself delayed by Δt.

 

[JoannesPaulus]

TSPC sizing

Use minimum size transistors and increase the size of the transistor closest to the power supply when there are two transistors in series between the input and output.

 

[ideal world]

TSPC sizing

@ AdvaRes
good sizing can ensure that but i can't get that sizing

@ JoannesPaulus
does this overcome charge sharing and all the problems of tspc
moreover what about at what ratio should i increase the transistors near the power supply

thanks

 

[JoannesPaulus]

Re: TSPC sizing

does this overcome charge sharing and all the problems of tspc

No.

moreover what about at what ratio should i increase the transistors near the power supply

I would start from twice the minimum width and increase by adding fingers until you are happy with the performance. I do not know of any analytical procedure for tspc sizing.