How to simulation Verilog HDL model using HSPICE?

[RDRyan]

hspice .hdl

I have made a RTL model with Verilog HDL. My question is: Can we transfer Verilog RTL model to netlist that can be run by HSPICE? which EDA tools do I need? and how to do it?

Thanks very much!

Ryan

 

[Teddy]

hspice .hdl cadence

Spice does not run verilog. Spice can run VerilogA. To run this you need mixed signal environment like AMS or ADMS

 

[RDRyan]

.hdl hspice

thanks for your comment.

And can we transfer Verilog HDL model to EDIF files, and use other tools (like viewdraw) to open it, then use viewdraw to create netlist that can be run in hspice ?

Ryan

 

[chenjia]

hspice cadence ahdl model

Cadence can do this job

 

[RDRyan]

Thank you, I will try to use cadence.

 

[skymusic]

In Cadence ADE, you can use hspiceverilog simulator to simulate verilog+schematic.
1 create a cell contain verilog file(using functional view)
2 create schematic view of test_bench cell connecting verilog cell and schematic cell.
3 create config view for test_bench cell
4 Open config view of test_bench cell, then open ADE to simulate