how to simulate VCO phase noise sensitive to power supply

[john.dcheng]

Hi All,

I designed a LC VCO, I can simulate phase noise of VCO, but I was asked to simulate phase noise sensitive to power supply decoupling. Any suggestion how to simulate? Thanks in advance.

John

 

[biff44]

depending on if it was a linear or switching power supply, you would AC couple white noise or spike noise onto the DC line, and see what phase noise rise happens in the oscillator output

 

[WimRFP]

Power supply variation will likely change the output amplitude and frequency of the oscillator. What simulator are you using?

To see the steady state sensitivity ( d(freq)/d(supply voltage) and d(amplitude)/d(supply voltage) ), simulate your oscillator at two supply voltages (for example Vnom and Vnom-5%). This will show you the sensitivity for slow power supply variations.

Very likely you want to run the amplitude and frequency response to a supply voltage step change. From the amplitude and frequency change versus time, you can assess the amplitude and frequency sensitivity for power supply variations in the frequency domain.

So if you simulated 10 kHz frequency change due to a supply voltage variation of 100 mVp at 100 Hz, and the actual supply ripple at 100 Hz is 10 mV, you can see that your oscillator is frequency modulated with 1 kHz. This frequency modulation adds to the phase noise (use first order Bessel functions).

 

[saro_k_82]

Do a pxf analysis and plot the outputs from the control voltage source (Signal) and the power supply (Noise). Look for the "-1" ref sideband to observe the frequencies that matter. Note their relative levels and model it as noise at the input of the VCO (or at the output) in the phase domain LTI model to see the closed loop phase noise profile which can be converted to jitter.
Make sure that the control voltage is referred to the correct supply before performing the simulation.

Alternatively as a quick rough estimate, you could run a transient with a sine wave of about 100mV amplitude at the supply of frequency equal to the bandwidth of the PLL (with dc control voltage) and compute the resulting jitter (by integrating only the first half of the cycle). This is the worst case jitter expected (for 100mV supply noise) due to supply pushing as the loop rejects noise below this frequency and above this frequency the noise gets attenuated in the supply bypass network (well, we hope)