Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How to simulate the sensitivity of CML latch

Status
Not open for further replies.

bageduke

Advanced Member level 4
Joined
Oct 19, 2005
Messages
119
Helped
11
Reputation
22
Reaction score
2
Trophy points
1,298
Activity points
2,093
I always saw some papers that showed the sensitivity curves when they used CML latch as frequency divider. I am wondering how they simulated this kind of curves.

What I can imagine is that they fixed the input frequency, swept input voltage, and then found out what the minimum voltage level to make divider work. After this, they changed to another frequency and repeated above steps until the whole frequency range was simulated.

Am I right, or there is another easier way to do it?

Thanks a lot
 

krashkealoha

Full Member level 1
Joined
Jul 3, 2004
Messages
99
Helped
15
Reputation
30
Reaction score
7
Trophy points
1,288
Location
21.402, -157.739
Activity points
1,292
Yes, you are correct. You also might want to force either a pulse or sine wave at the input and see what the difference in input sensitivity you will get.
 

2steps

Newbie level 6
Joined
Aug 3, 2006
Messages
13
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,352
Thanks, that is my question!
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top