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How to simulate the offset of the clocked comparator?

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Junior Member level 2
Sep 8, 2009
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Does anybody know how to simulate the offset of the clocked comparaor?
I really need the help , please!

If this is a traditional compartor, you can run a DC simulation whereby you tie the negative input to the output and put a DC voltage at the positive terminal. The DC sim will converge easily if there isnt a latch (or hysteresis). If you can get the sim to converge then you can get the offset rather easily by reding the output voltage with this amp-like configuration. If you want the offset of the compartor without the latch, you can remove the latch and just sim the comparator and the get the offset using the above described method. Now, keep in mind that if you run a transient with this method you will make the comaparator oscillate. This is just for sim purposes.


Here is a waveform you could use to check the offset of a clocked comparator. The small steps should be 0.5LSB and the big steps should be at least a couple of LSBs (so that you can check for hysteresis as well).

I hope this helps.

i m simulating the offset voltage of cmos clocked comparator on tanner, would u plz tell me the netlist of this waveform?

Perhaps you want to simulate it, the way you would test
it in an ATE environment. That is, wrap an integrator around
the whole thing, making it a negative feedback system.
Then you run the clock as normal, you apply an input
voltage to the "free" terminal and you read the input difference
voltage after you've had enough clocks to settle the integrator
to a stable output.

If you use equal resistor dividers on the input and integrator-
feedback paths this will help you work at lower offsets
in a noisy test environment, and you can take your measurement
off the integrator output before the down-scaling for a more
robust signal.

This is a paper about the method for accurately determining DC and dynamic offsets in the clocked comparators, I hope it would be helpful for you.

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