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How to simulate the clock generators in LTSPICE for an ADC

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fgjh

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I am trying to build a clocked comparator. The preamplifer stage is built using switched capacitors. I have a circuit to generate these clock which should be given to the MOS transistors. How do I tie the clock into the LTSPICE model I am building for the comparator?
 

crutschow

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Your comparator model needs an input for the clock to enable the comparator.
Since you didn't post the model you have and I'm not clairvoyant, I cannot make a more detailed suggestion.
 

fgjh

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Maybe I worded my orginal post incorrectly. I am building a comparator from MOS transistors and trying to simulate them . However for the first sample and hold stage using switched capacitors, I need to provide a clock to the MOS transistors themselves. But the clock is generated using verilog code. I have the circuit level diagram if I need to enter it in manually. My question is how do I use this clock with the verilog code in LTSPICE?
 

FvM

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In case of doubt, you'll use an independent voltage source (V component) with PULSE settings.
 

fgjh

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But the problem is that it involves a lot of work to accurately get each of the pulses to meet the verilog constraints. I already have the verilog code and would like to know if there is a way to get the 2 to work together?
 

FvM

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There's no Verilog co-simulation in LTSpice.

I don'z however exactly understand the problem. You are talking about a single, continuous clock which is defined by a few parameters?
 

fgjh

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Okay . Thanks for the help. There is more than one clock though. In switched capacitors the clocks control which transistors turn on
 

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You've been talking about "clock" rather than "clocks" in your initial post.

An alternative could be to convert a ModelSim list file to a LTSpice wavefile source. But if your Verilog clock generator is essentially a simple infinite loop, it can be better represented by PULSE sources.
 
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