how to simulate Spur in PLL loop

[hearter]

it is time consuming, We can simulate .tran output freq and do FFT, but I know there must be better way to do. also can we predict spur based on loop dynamics? say Icp mismatch 1%, PFD error 1%, charge injection average 0.1uA over time. loop BW 1M, Fref=20MHz. VCO out 500MHz etc.

any insig is appreciated.

 

[dick_freebird]

Only to the extent that the loop is responsible for the spurs.
From fluttering about the edges, I see some components
of phase noise that are internally generated (esp. supply
rail activity and phase detector signal risetimes, these
create small jitters and close-in phase noise that the loop
can only roll off slightly).

Faster, perhaps; faster and more accurate, probably not.