haha, when i reply ur msg, i start to ask myself about the phase noise simulation in mentor graphic.
because i also havent tried out this before. can you wait for few day? when i go lab only can try to do the noise simulation.
i read the book from B.Razavi. Phase noise of VCO is higher than PFD. really sorry, lab close on weekend.
i had just done my PFD with dead zone elimination architecture with input frequenc 100MHz only. if i try out more simulation, we can have some discussion.
i also a new guy to IC design and PLL.