There is a canonical HBM ESD model. In simulation it's easy to
modify it such that the switch and capacitor are replaced with
a pulse source and series cap of same value. You could then
extend this to parameterized sources to enable full pin-pin ESD
performance analysis.
But it all depends on having a decent model of the clamp and
back-diode elements, which is not always available in the foundry
PDK.
Using a TLP and 'scope you can get short-time breakdown and
series resistance fitted. I use a degenerate zener model (forward
I-V and capacitance params are zeroed, so as not to affect the
presumably well modeled core clamp FET forward characteristics)
and fit the reverse characteristics so that the composite, clamp
+ "breakdown model", matches bench.
ESD clamps will walk in or walk out with repetitive stress. The
good ones will walk out (breakdown voltage increase, leakage
decrease) asymptotically; one that does the opposite is
unreliable and a poor choice. Maybe you only get one though.
Begin with the simple problem - does, or does not your clamp
element show a reasonable breakdown I-V, or is better than
reasonable (i.e. accurate)?
Now if you want to impress, find a way to simulate the Joule
energy shed in the clamp and its adiabatic temperature rise
(depending on device thermal mass <- volume <- params &
vertical details - SOI, etc.). And pay heed to current crowding
and the parasitic resistance mesh, which determine how well
you spread the power to keep the peak temp below damage
threshold. Of course you don't know this limit a priori, you
would determine it by a pulsed-power-to-blow series of zaps
on some test device, or devices employing different layout
styles to gauge best practices.