Non AMP

How to set the core_gen signal ?

Thread starter kun
Start date Nov 5, 2007

Status: Not open for further replies.

Feb 25, 2008

#21

A

apv1965

Junior Member level 2

core_gen

Is your peoblem solved? Can you give some more explanations and clearity about what exactly U want and what is the application?

Status: Not open for further replies.

Similar threads

H
How to store Coco training data set in Pynqz2 board
- Started by hudda
- Saturday at 12:10 PM
- Replies: 1
PLD, SPLD, GAL, CPLD, FPGA Design
S
how to set global include in synplify, like vivado "set global include"
- Started by skyworld_cy
- Dec 21, 2023
- Replies: 5
PLD, SPLD, GAL, CPLD, FPGA Design
S
Image fusion how to implementing on FPGA
- Started by Sanila P
- May 14, 2024
- Replies: 1
PLD, SPLD, GAL, CPLD, FPGA Design
M
How to instantiate another vhd file inside testbench, where the testbench is used for opening files
- Started by metamisers
- Jan 6, 2024
- Replies: 6
PLD, SPLD, GAL, CPLD, FPGA Design
K
explanation of how to translate C code into verilog
- Started by keikaku
- Mar 5, 2024
- Replies: 10
PLD, SPLD, GAL, CPLD, FPGA Design