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How to send same signal to different modules in VHDL

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xilinx1001

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Hi,

I need to give same signal to 2 different modules in VHDL


Can anyone suggest something about this


Thanks in advance

xilinx1001
 

shaiko

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What is the problem exactly??
Assign the signal to the component at question when you instantiate it.
 
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sivamani

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map the signal in the component instantiation module where u would like to pass the signal..
 

xilinx1001

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Hi,

Thanks for your reply. I have the problem just like this

This is my entity

entity uartl is
Port ( TXD : out std_logic := '1';
RXD : in std_logic := '1';
CLK : in std_logic;
LEDS : out std_logic_vector(7 downto 0) ;
RST : in std_logic := '0';
trig1 : out std_logic;
trig2 : out std_logic;
tclk:inout std_logic;
segment: out std_logic_vector(8 downto 0);
cm:in std_logic_vector(8 downto 0);
cm2:in std_logic_vector(8 downto 0)
);
end uartl;

I am giving cm and cm2 signals to display by port mapping like this cm=>segment; cm2=>segment;

when I am giving cm signal to display a character "s" must display and

when I am giving cm2 signal to display a character "t" must display

I am able to do "s" and I am able to display other sensor reading also

But my problem is how can I display "t"

How can I do that


Thanks in advance
xilinx1001
 

shaiko

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post your whole code

- - - Updated - - -

and please use the appropriate tag for your code (#) - so it'll be easier to read.
 

xilinx1001

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Hi,

I am posting my code here:



Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity uartl is
	Port ( 	TXD		: out std_logic := '1';
		 	RXD		: in std_logic 	:= '1';
		  	CLK		: in std_logic;
			LEDS	: out std_logic_vector(7 downto 0) ;
		  	RST		: in std_logic	:= '0';
			trig1 : out std_logic;
			trig2 : out std_logic;
			tclk:inout std_logic;
			segment: out std_logic_vector(8 downto 0);
			cm:in std_logic_vector(8 downto 0);
	      cm2:in std_logic_vector(8 downto 0)
			);
end uartl;

architecture Behavioral of uartl is


component RS232RefComp
   Port (  	TXD 	: out	std_logic	:= '1';
		 	RXD 	: in	std_logic;					
  		 	CLK 	: in	std_logic;							
			DBIN 	: in	std_logic_vector (7 downto 0);
			DBOUT 	: out	std_logic_vector (7 downto 0);
			RDA		: inout	std_logic;							
			TBE		: inout	std_logic 	:= '1';				
			RD		: in	std_logic;							
			WR		: in	std_logic;							
			PE		: out	std_logic;							
			FE		: out	std_logic;							
			OE		: out	std_logic;											
			RST		: in	std_logic	:= '0';
			tclk:inout std_logic);				
end component;	
-------------------------------------------------------------------------
--
--Title:	Type Declarations
--
--Description:	There is one state machine used in this program, called 
--				the mainState state machine.  This state machine controls 
--				the flow of data around the UART; allowing for data to be
--				changed from serial to parallel, and then back to serial.
--
-------------------------------------------------------------------------
	type mainState is (
	stReceive,
		state1,
		state2,
		state3,
		state4
		  );

-------------------------------------------------------------------------
	signal dbInSig	:	std_logic_vector(7 downto 0);
	signal dbOutSig	:	std_logic_vector(7 downto 0);
	signal rdaSig	:	std_logic;
	signal tbeSig	:	std_logic;
	signal rdSig	:	std_logic;
	signal wrSig	:	std_logic;
	signal peSig	:	std_logic;
	signal feSig	:	std_logic;
	signal oeSig	:	std_logic;
	
	
	signal stCur	:	mainState := stReceive;
	signal stnext	:	mainState;



begin


	LEDS(7) <= dbOutSig(0);
	LEDS(6) <= dbOutSig(1);
	LEDS(5) <= dbOutSig(2);
	LEDS(4) <= dbOutSig(3);
	LEDS(3) <= dbOutSig(4);
	LEDS(2) <= dbOutSig(5);
	LEDS(1) <= dbOutSig(6);
	LEDS(0) <= dbOutSig(7);

	UART: RS232RefComp port map (	TXD 	=> TXD,
									RXD 	=> RXD,
									CLK 	=> CLK,
									DBIN 	=> dbInSig,
									DBOUT	=> dbOutSig,
									RDA		=> rdaSig,
									TBE		=> tbeSig,	
									RD		=> rdSig,
									WR		=> wrSig,
									PE		=> peSig,
									FE		=> feSig,
									OE		=> oeSig,
									RST 	=> RST,
									tclk=>tclk);


process (tclk, RST)
		begin
		if (tclk = '1' and tclk'Event) then
			
				if RST = '1' then
					stCur <= stReceive;
				else
					stCur <= stnext;
					
				end if;
			end if;
		end process;


	process (tclk,stCur, rdaSig, dboutsig)
	--stCur, rdaSig, dboutsig,
	begin
	if (tclk'Event and tclk = '1') then
	
		
			[B]case stCur is

                when stReceive =>
                    rdSig <= '0';
                    wrSig <= '0';

                        if rdaSig = '1' then
								
                        if (dbOutSig = X"73") then  --s
			 
								trig1 <='1';
                        dbInSig <= (15 downto 9=> '0')& cm2(8);
			segment<= cm2(8 downto 0);
								
								
                        stnext <= state1;
                       elsif (dbOutSig = X"74") then --t
          
						      trig2 <='1';
								
                      dbInsig <=  (15 downto 9=> '0')& cm(8);
		     segment<= cm(8 downto 0);
							 
                        stnext <= state1;
                       else
                       stnext <= stReceive;
                        
                    end if;    
                    end if ;  
                    					  [/B]
-------------------------------------------------------------------------
--
--Title: stSend state 
--
--Description:    This state tells the UART to send the parallel 
--                information found in dbInSig.  It does this by strobing 
--                both the rdSig and wrSig signals high.  Once these 
--                signals have been strobed high, the stReceive state is 
--                loaded.
--
-------------------------------------------------------------------------
                when state1 =>
                    rdSig <= '0'; 
                    wrSig <= '1';
                    stnext <= state2 ;
                    
                    
                 when state2 => 
       
                  rdSig <= '0';
                  wrSig <= '0';
						if (dbOutSig = X"74") then
						dbInsig <= cm( 7 downto 0) ;
						end if;
						if (dbOutSig = X"73") then
						dbInsig <= cm2( 7 downto 0) ;
						end if;
						stnext <= state3 ;
						
						when state3 => 
       
                  rdSig <= '0';
                  wrSig <= '1';
						stnext <= state4 ;
						
						when state4 => 
       
                  rdSig <= '1';
                  wrSig <= '0';
						
						stnext <= stReceive ;
    
            end case;
          end if ;
       end process;
        
        

end Behavioral
;


You can see in the second process of the code, when (dbOutSig = X"73") I am giving the sensor data to segment


I am port mapping the segment with the input of display in the top module

But , how can I display the other sensor reading

Thanks
xilinx1001
 
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