How to select a beta value for cell library

[Prashanthanilm]

Hi All,

Given .Wn+Wp=700n

With Simulations I am able to get less delay for:
InvMOS=360 nMOS=340
NandMOS=310 nMOS=390
NORMOS=420 nMOS=280

Now How can I choose the beta value for the cell libraries?.

Any help would be really appreciated.

Thank you
Prashanth

 

[OhaAmo]

Well, you have several option.
If you are using a vendor library, you have limited options while using already-made cells with alternate driving strengths (X1,X2 ...).
If you are creating a custom made library, you can have different beta for each gate, based on the simulations results you got.
If you need 1 and only beta for the entire library you have to either make simulations that will average the 3 different betas you got or to calculate it yourself.

 

[Prashanthanilm]

Well, you have several option.
If you need 1 and only beta for the entire library you have to either make simulations that will average the 3 different betas you got or to calculate it yourself.

'

Yes, what if I need only one for the entire library. I have given the values for inverter , NAND and NOR . Can you suggest me what beta value should I take by looking in to those 3?.
Given Wn+Wp=700n

 

[OhaAmo]

If I remember correctly, typical beta is around 2.5-3, because of electron higher mobility as compared to holes mobility in pmos.
There are many academic articles about the subject.
Pay attention that beta is dependent on target chip manufacture process.

BTW - You should double check the results you got. Beta should be around the same value for those 3 gates above. Maybe something was wrong with your simulation.

 

[Prashanthanilm]

If I remember correctly, typical beta is around 2.5-3, because of electron higher mobility as compared to holes mobility in pmos.
There are many academic articles about the subject.
Pay attention that beta is dependent on target chip manufacture process.

BTW - You should double check the results you got. Beta should be around the same value for those 3 gates above. Maybe something was wrong with your simulation.

Yes , the nMOS mobility is more so the pMOS width is more.

I think the beta value changes with respect to NAND and NOR. Because of the parallel connections and all.

 

[OhaAmo]

beta is the ratio between the PUN to the PDN. Sizing the transistors may be different, but beta itself is about the same.
For example -
NAND has got 2 parallel transistors in the PUN. if you will choose single width of them, you will get PUN in the strength of 2 because they are in parallel. in order to get beta = 2 for instance, you will need double width of the 2 nmos transistors because they are in series.

 

[Prashanthanilm]

Yes, Correct. I mentioned in the wrong way. But the simulation result is correct.

For worst case :420+390=810.. It cannot be done because the max allowance is 700n.

So, with this 3 simulation results I have to find out the beta value( as of now).

How can I do this?
Is there any defined procedure for this?.

Just confused with this stuff.