How to sample a pulse or a clock into memory?

I am using Zynq development board, on which I am generating some kind of pulse inside PL. I want to sample this pulse/clock into RAM to be able to read it from software on the PS core (to get sort-of oscilloscope view).

Since my pulse is currently being generated at about 100-200MHz, I guess I will need to down sample it to something slower for PS software to be able to capture it.

How do I do that in verilog?

Do the pulses appear spread out far enough apart that you will be able to finish processing the first pulse before the next pulse?

If the answer to the above question is yes, then a simple toggle FF could be used to generate an input to the PS from the 100-200MHz domain. In the PS you check if the signal changed from low-high or high-low (edge detect). Or you could use the strobe to generate an interrupt. The pulse sets a FF (the interrupt) and then the interrupt routine can clear the FF.

If the answer is no and you need to queue the pulses, then you could add a FIFO to store each strobe until you have a chance to read it. Once again this could be level or interrupt driven.


The Verilog would be directly derived from the above circuits that I described.

Thank you.
In my case its no. So I need to use asynchronous FIFO with 100-200MHz clock and something like 25MHz clock?

Yes you would need to use a FIFO in that case. I would assume you use whatever bus clock or interface clock is used on the PS. I haven't looked too much into the Zynq so I'm not familiar with the details of the possible interfaces you can take advantage of between the PS and PL.